Integrated circuits have substantially increased in complexities over the years. The technology is moving towards smaller and smaller device structures. The extension of the technology to obtain narrow line widths in the range of 1 micrometer or less by extending conventional photolithography techniques such as electron beam, ultraviolet light, or X-ray lithography is becoming more difficult and expensive.
Other narrow device structure techniques have been developed to overcome this problem. One such technique is described in H. B. Pogge in IBM Technical Disclosure Bulletin, November 1976, Vol. 19, No. 6, pgs. 2057-2058 entitled "Narrow Line Widths Masking Methods". This method involves the use of a porous silicon followed by the oxidation of the porous silicon. Another technique is described by S. A. Abbas et al., in the IBM Technical Disclosure Bulletin, September 1977, Vol. 20, No. 4, pgs 1376-1378. This method describes the use of polycrystalline silicon masking layers which are made to mask by first using an intermediate mask of oxidation blocking material, such as silicon nitride in the formation of the polycrystalline silicon. Line dimensions below about 2 micrometers may be obtained by this technique.
Methods for forming narrow dimensioned, for example, sub-micrometer regions on the silicon body are disclosed by U.S. Pat. Nos. 4,209,349 and 4,209,350 by I. T. Ho et al., and U.S. Pat. No. 4,234,362 by J. Riseman. These patents involve the formation of substantially horizontal surfaces and substantially vertical surfaces on the silicon body and then forming a vertical layer of a very narrow dimension on the substantially vertical surfaces. This layer may be formed by initially depositing a very narrow dimensioned layer on both the substantially horizontal and substantially vertical surfaces followed by an anisotropic reactive ion etching process to remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied. Alternatively, the vertical layer may be formed by the oxidation of a side edge of a polysilicon layer which has its top surface masked by a oxidation resistant coating such as silicon nitride as described in the S. G. Barbee et al., IBM Technical Disclosure Bulletin, Aug. 19, 1982, Vol. 25, No. 3B, pgs. 1448-1449 or as shown in the H. B. Pogge, U.S. Pat. No. 4,256,514. In these ways a narrow dimension region of one micrometer or less may be obtained.
A further major related problem in the very dense integrated circuit technology is how to electrically contact the various elements and devices of such narrow dimensions in the integrated circuit. It is known to use highly doped polycrystalline silicon as a source of a dopant for regions of monocrystalline silicon to form PN junctions therein. The polycrystalline silicon can either be removed or allowed to become part of the device as the electrical contact for the region formed by the out-diffusion from the polycrystalline silicon. Such processes are taught, for example by D. M. Duncan, U.S. Pat. No. 3,978,515; J. H. Scott, Jr., U.S. Pat. No. 3,460,007; D. M. Duncan, U.S. Pat. No. 3,664,896; S. Tauchi et al., U.S. Pat. No. 3,484,313 and the aforementioned I. T. Ho et al., U.S. Pat. No. 4,209,350. However, these patents are either silent on the method for the next level metallurgy to the electrical contact or have a second level metallurgy directly above the polycrystalline silicon electrical contact to the PN junction.
Other workers in the field have addressed the electrical contact in other ways, such as U.S. Pat. No. 3,600,651, by providing lateral polycrystalline silicon contacts to a monocrystalline silicon active region. The polycrystalline silicon is then contacted at a more convenient location laterally away from the active region. N. G. Anantha et al., U.S. Pat. No. 4,236,294 also uses the technique of a polycrystalline silicon contact to a PN junction and then a contact to the polycrystalline layer at some convenient distance laterally away from that PN junction. The H. S. Bhatia et al., patent application Ser. No. 405,844 filed Aug. 6, 1982 entitled "Method For Contacting A Narrow Width PN Junction Region and Resulting Structure" describes further methods for making contact to a narrow width PN junction region by electrically contacting a horizontal conductive layer at a convenient location. The horizontal conductive layer in turn contacts a vertical conductive layer which makes contact to the element of the integrated circuit.
It is an object of the present invention to provide methods and resulting structures for forming a lateral bipolar transistor which is even smaller than those envisioned in the prior art technologies.
It is further object of the invention to describe methods of forming closely spaced openings to a semiconductor surface which may in turn be utilized to form elements in the semiconductor surface for use in very dense integrated circuit structures.